专用集成电路与系统国家重点实验室讲座信息

时      间：2015年1月29日周四上午9:30-10:30
地      点：张江校区微电子楼389室
讲座题目：Humanistic Intelligence System(Multi-core Pattern Recognition Processor with Mixed mode Neuro-Fuzzy Circuits)
报 告 人： Prof. Hoi-Jun Yoo（KAIST，Korea）

Abstract
Multi-core processors are useful for the real-time pattern recognition for car navigation, autonomous robot, surveillance camera, and humanistic interface to consumer products.
In this lecture, the benefits and methods of the integration of the neuro-fuzzy logic or soft-computing with multi-core processor will be explained, especially for high speed low power pattern recognition application. Analog-digital mixed mode neuro-fuzzy logic circuits are integrated with multi-cores to provide the ‘attention’ of the cluttered view to speed up the recognition process and improve its accuracy. In addition, learning in the neuro-fuzzy logic enables to adapt its operation to the input over time. The various multi-core architectures are implemented with the help of high performance Network on Chip, and the low power schemes such as DVFS and gate control. System demonstrations such as autonomous robot, car navigation, and life-log such as K-Glass will be introduced.

Bio
Prof. Hoi-Jun Yoo is the full professor of Department of Electrical Engineering at KAIST, the director of SDIA(System Design Innovation and Application Research Center) and the leader of Dr. M project (KAIST Mobile Healthcare Project). From 2003 to 2005, he was the full time Advisor to the Minister of Korean Ministry of Information and Communication for SoC and Next Generation Computing. His current research interests are Bio Inspired IC Design, Wearable Computing and Wearable Healthcare. He published more than 200 papers, and wrote 5 books including "Biomedical CMOS ICs"(2011, Springer).
Dr. Yoo received the National Medal for his contribution to Korean Memory Industry in December of 2011, the Korean Scientist of the Month award in Dec. 2010, Best Research of KAIST Award in 2007, Design Award of 2001 ASP-DAC, and Outstanding Design Awards 2005, 2006, 2007 A-SSCC. He is an IEEE Fellow, a member of the executive committee of ISSCC, Symposium on VLSI, and A-SSCC. He was the TPC Co-Chair of ISWC 2010, IEEE Distinguished Lecturer('10-'11), and Asia Chair of ISSCC(‘10-‘11). He is TPC Chair of ISSCC 2015 and recognized as the top 4 paper-contributor for 2004-2013 ISSCCs and top 10 paper contributor for 1954-2013 ISSCCs.