时  间：2015年11月18日上午10:00
地  点：张江校区微电子楼389室
演讲人：Dr. Dhiraj Goswami Synopsys Fellow in Hillsboro Oregon, USA
        Dr. William N. N. Hung , Principal Engineer at Synopsys in Mountain View, California

 
Abstract
Five decades ago, Moore‘s law predicted the exponential growth of the semiconductor industry. Over the years, the increasing design complexity has called for effective and comprehensive verification of hardware and embedded systems. Functional verification has become a key concern in hardware and software system development. It is generally believed the majority of design effort is spent in functional verification, whose complexity explodes as the size of the design increases. The increasing adoption of high-level synthesis brings the consistency of C++ / System C / high-level model and register-transfer-level model into the picture. With the emergence of embedded system, functional verification of embedded software also becomes a key concern for the industry.
There are many approaches for functional verification: formal verification, dynamic verification, hardware emulation, hardware prototyping, etc. At present, constraint-based dynamic verification is still the mainstream approach in industry, especially for large complex designs. Dynamic verification is conducted by feeding input patterns to the design and simulating its behavior against a specification checker. The exponential nature of input patterns means, however, only a small subset of them can be sampled for dynamic verification. To quantify the extensiveness of dynamic verification, functional coverage is a criterion widely used. How to improve functional coverage is a key challenge to the industry.
In this talk, we will survey industrial standards, tools and methodologies to tackle the above verification problems, including the industry wide shift-left campaign, from software to hardware, formal, semi-formal, and constraint-based verification, accelerations, new ways of debugging and tackling complexity issues, ways to improve functional coverage, as well as new initiatives in software verification.

Biography
Dhiraj Goswami received his B.Tech degree from Indian Institute of Technology Kanpur and his MS degree from the University of Southern California. He has over 20 years of R&D experience in Electronic Design Automation, encompassing product development, design flow development, technical innovation, and defining technical strategy. He is currently a Synopsys Fellow in Hillsboro Oregon, USA, and he is the architect of emulation front-end in ZeBu, the synthesis solution in Verification Compiler, and the constraint random verification solution in Verification Compiler. He has received numerous awards over the years, including the Intel Discovery Award, the Synopsys Excellence Award, and the Synopsys Top Inventor Award. He served as a member in the IEEE standards committee on System Verilog. He has 15 patents.
William N. N. Hung received his B.S. degree and M.S. degree from the University of Texas at Austin and his Ph.D. from Portland State University. He is currently a Principal Engineer at Synopsys in Mountain View, California, leading technological innovations on constraint based verification and hardware accelerated verification such as emulation and prototyping. He has over 18 years of industrial R&D experience, and has 9 patents and more than 80 publications. Dr. Hung served as Chair of the Quantum Computing Task Force of the IEEE Computational Intelligence Society, and as Co-Chair of the Logic & Circuit Track in the Technical Program Committee of ICCD. He served on the Technical Program Committee for many conferences including Design Automation Conference (DAC), Computer Aided Verification (CAV), FMCAD, etc. He was an invited (keynote) speaker at CAV 2015.