| 系列讲座信息 X. Sharon Hu,General Chair of DAC 2018, IEEE Fellow will visit Fudan Univ. 1. Cellular Neural Network Friendly Convolutional Neural Networks
时间：2017年7月18日下午3:30-5:00
地点：微电子楼269会议室 Abstract:
This talk discusses the development and evaluation of a Cellular Neural Network (CeNN) friendly deep learning network for solving the MNIST digit recognition problem. As a representative locally connected and highly parallel architecture, cellular neural networks (CeNNs) are under investigation via the Semiconductor Research Corporation (SRC)’s benchmarking activities. Prior work has shown that CeNNs leveraging emerging technologies such as tunnel transistors can improve energy or EDP of CeNNs, while simultaneously offering richer/more complex functionality. Important questions to address are what applications can benefit from CeNNs, and whether CeNNs can eventually outperform other alternatives at the application level in terms of energy, performance, and accuracy. This talk elaborates using CeNNs to realize convolutional neural networks (CoNNs) and applying a CeNN-friendly CoNN to a standard inference problem, i.e., MNIST digit classification. Initial accuracy/energy/delay projections for the CeNN approach is then compared with other projections for the same problem from the published literature. Results show that CeNNs can be a competitive alternative for accomplishing certain learning networks.
2. Exploiting Ferroelectric FETs: Faster and Cooler Non-Volatile Logic-In-Memor
时间：2017年7月19日下午2:30-3:30
地点：微电子楼269会议 Abstract:
The inevitable slowdown of the CMOS scaling trend has fueled an explosion of research endeavors in finding a CMOS replacement. However, recent studies suggest that many of the emerging transistors being investigated, if used as simple drop-in replacement for MOSFETs, may only achieve speedups that mirror historical trends in the best case. The consensus from the community is that cross-layer efforts are essential in combating the CMOS scaling challenge. This talk presents such an effort centered around a particular emerging device, ferroelectric FETs (FeFETs).
An FeFET is made by integrating a ferroelectric material layer in the gate stack of a MOSFET. It is a non-volatile device that can behave as both a transistor and a storage element. This unique property of FeFETs enables efficient and low-power fine-grained in-memory computing, which are desirable for many data analytics and machine learning applications. This presentation will elaborate novel circuits based on FeFETs to accomplish basic logic-in-memory operations, ternary content addressable memory (TCAM) as well as basic elements in FPGAs. Architectural level evaluation of using FeFET TCAM in a GPU system will also be discussed.
3. Introduction of Design Automation Conference
时间：2017年7月20日下午2:30-3:30
地点：微电子楼269会议
介绍Design Automation Conference (DAC).
Bio
Sharon Hu is a professor in the department of Computer Science and Engineering at the University of Notre Dame, Notre Dame, Indiana, USA. Her research interests include low-power system design, circuit and architecture design with emerging technologies, hardware/software co-design and real-time embedded systems. She has published more than 270 papers in these areas, and received the Best Paper Award from the Design Automation Conference in 2001 and from the IEEE Symposium on Nanoscale Architectures in 2009. She is the Vice General Chair of Design Automation Conference in 2017. She also served as Associate Editor for IEEE Transactions on VLSI, ACM Transactions on Design Automation of Electronic Systems, ACM Transactions on Embedded Computing Systems. Sharon Hu is a Fellow of the IEEE. 联系人：杨帆 |